1. Field of the Invention
The present invention generally relates to a clock distribution network design for high speed microprocessors and other very large scale integrated (VLSI) circuits and, more particularly, to a clock distribution network with dual clock lines to drive the clock network in a way that significantly reduces clock skew without paying a penalty of large wiring areas and consequently enormous power consumption.
2. Background Description
Integrated circuit manufacturing technology has made great advances in reducing the feature size on the one hand and enlarging the die size on the other hand. The increase of the chip size coupled with the requirement of faster clock period imposes the following challenging problem for the clock design: How can we design a clock network which properly synchronizes the latch operations on the different parts of a very large semiconductor integrated (VLSI) circuit chip? This requires that the clock skews, the difference of clock arrival times at clock pins, be reduced to some tolerable fraction of the cycle period.
A popular approach to the clock design problem in the literature is to generate a mesh structure clock network, as illustrated in FIG. 1. With a mesh structure comprising, in the example illustrated, a main clock line 11 and branching clock lines 12.sub.1 to 12.sub.5, the network can deliver clock signal to any latch designers might place on the chip. The connection to the clock pins of latches is through some inverter buffers 13.sub.1 to 13.sub.8. The inverter buffers are needed to drive several latches (not shown) in the same neighborhood.
As deep sub-micron technology emerges, signal delays over long narrow wires become more prominent, about 100 picoseconds (ps) for 5 millimeter (mm) line in today's complementary metal oxide semiconductor (CMOS) technology. Also, it is well known that narrow lines are more susceptible to process variations, which causes the minimum wire width to vary from one side of chip to the other. Therefore, in order to control the resulting skew problem, the clock wires in the mesh structure need to be fattened in the entire chip area. The fat wires will decrease the delay from the clock source to inverter buffers, and thus also reduce the skew. Digital Equipment Corporation's Alpha processor adopted this approach. The drawback is that these fat wires take a large area of the metal layer and also consume enormous power. A way to reduce skew without the area and power penalty becomes a major goal of high speed microprocessor design.